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This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for...
A highly linear, 3rd order, active-RC low-pass elliptic filter with Variable Gain Amplifier (VGA) is presented. The new derivative-free biquad topology for an elliptic filter could be easily extended to a higher order filter using a cascade of biquads and it will have a zero capacitive spread when used along with a VGA. It is introduced to minimize the power consumption of an active-RC filter in a...
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