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Ring oscillator (RO) based physical uncloanble function (PUF) is an emerging hardware security primitive but its response is susceptible to changes in operating conditions. Current solutions either incur large hardware overhead or require sophisticated RO selection algorithms to increase its reliability. This is the first paper that exploits the temperature invariant biasing of three different types...
Efficient modular adders and subtractors for arbitrary moduli are key booster of computational speed for high-cardinality Residue Number Systems as they rely on arbitrary moduli set to expand the dynamic range. This paper proposes a new unified modular adder/subtractor that possesses a regular structure for any modulus. Compared to the latest modular adder/subtractor, which works for modulus in the...
Sign detection is a necessary but non-trivial operation in Residue Number System (RNS) for many digital signal processing applications. Efficient sign detector for the three-moduli set RNS {2n −1,2n, 2n +1} has been proposed, but the problem remains unsolved for its extended four moduli sets. This paper presents a new sign detection algorithm dedicated to {2n −1,2n, 2n +1,22n +1} RNS that has a wider...
This paper presents a new algorithm for the correction of single residue digit error in Redundant Residue Number System. The location and magnitude of error can be extracted directly from a minimum size lookup table. This is made possible by the introduction of a new syndrome, which is proven to be unique for every different residue digit error with two criteria imposed on the choice of redundant...
Scaling is used for wordlength reduction in many DSP algorithms. Variable scaler provides greater flexibility than fixed scaler and allows for more efficient utilization of the dynamic range. Programmable magnitude scaling is extremely difficult to perform in RNS, let alone scaling of signed integer. To the best of our knowledge, no programmable signed integer scaler in RNS has been reported. What...
Residue Number System (RNS) is often adopted to implement long and repetitive multiplications of cryptographic and signal processing algorithms. To sustain the competitive advantages of RNS over two's complement system in pervasive computing platforms, the hardware cost of parallel modulo arithmetic operations must be lowered. In this paper, new low power and low area modulo multipliers for the well-established...
This paper studies the performance of RNS-based inner product step processor of different special moduli sets. The processor is generic with programmable number of modulo additions and multiplications. Such processor is the core of FIR filters and FIR filter-like functions such as correlators, convolvers, DFT/FFT/DCT, etc. In our study, five different RNSs with modulo arithmetic friendly moduli of...
This paper presents a new approach to serial/parallel multiplier design by using parallel 1psilas counters to accumulate the binary partial product bits. The 1psilas in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to [log2 N]+1. This logarithmic reduction results...
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