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Metal gate/high-k CMOS technology for 28-nm node low power and low standby power application is demonstrated. A gate-first single metal/high-k gate stack has been employed together with leading-edge isolation, ultra-shallow junction, and stress engineering technologies. High density and high performance device is provided with least process cost increase.
A parallel core testing method, between-core vector overlapping testing, has been proposed for manufacturing testing of SoCs consisting of multiple cores. The testing method uses a test data sequence generated by overlapping the test vectors for the constituent cores, and tests the cores in parallel by the test data sequence. This method needs only a small number of LSI input pins for testing and...
A communication LSI for residential gateways has been developed. The LSI has an inline-IPsec circuit, which achieves 1 Gbit/s performance for both encryption and decryption, a small-scale high-speed look-up circuit in which only comparators are made parallel, and a hierarchical and reconfigurable QoS circuit. A 2 Gbit/s full wire rate throughput was achieved at a power consumption of 2 W.
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