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A parallel core testing method, between-core vector overlapping testing, has been proposed for manufacturing testing of SoCs consisting of multiple cores. The testing method uses a test data sequence generated by overlapping the test vectors for the constituent cores, and tests the cores in parallel by the test data sequence. This method needs only a small number of LSI input pins for testing and...
A communication LSI for residential gateways has been developed. The LSI has an inline-IPsec circuit, which achieves 1 Gbit/s performance for both encryption and decryption, a small-scale high-speed look-up circuit in which only comparators are made parallel, and a hierarchical and reconfigurable QoS circuit. A 2 Gbit/s full wire rate throughput was achieved at a power consumption of 2 W.
EOT reduction is a key challenge to keep the Moore's law, especially in low power LSIs. Nice candidates of gate dielectric as alternative to conventional SiO2 are N-rich SiON and high-K. However, in each case, we truly need tuning tools of Vth in the system LSI applications. F incorporation technique should be effective in Vth tuning with both N-rich SiON and high-K. Moreover, F incorporation is promising...
In this paper, the authors demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower Vth in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation Vth lowering up to ~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated...
An LSI module placement algorithm which uses neural networks is presented. A formula which determines the weighting factors of the constraint and objective function in the energy so that they converge to a vertex, a point on the edge, or an interior point of the hypercube is derived. In a comparison with simulated annealing and min-cut methods, the proposed method was as good as the min-cut method...
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