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This paper introduces an online precision spindle rotation error measurement system based on three point method. In this measurement system, the connection of software and hardware, data acquisition and processing, results displaying and saving and other functions have been realized. The feasibility and reliability of the measurement system have been proved by the measurement of a machining center...
In immersion lithography, a single exposure resolution of 36.5 nm half pitch (k = 0.255) has been demonstrated with a numerical aperture of 1.35. However the practical resolution limit in production will be closer to 40 nm half pitch (k = 0.28), without involving double patterning alike strategies, such as self-aligned double patterning (SADP). While for the practical resolution limit with k value...
With the appearance of different manufacturers and types of 1553B bus devices, the problem of the lack of real-time analysis and evaluation of effective tools for bus test method becomes severe. So a set of general configurable and flexible testing and simulating verification system for 1553B bus. In this thesis, a set of real-time hardware and software systems solution is proposed, a novel mechanism...
PCI Express is rapidly establishing itself as the successor to PCI, which provides higher performance, increased flexibility, and scalability for next-generation systems. FPGA offers a flexible solution for PCI Express compared with ASIC. Using IP Core and designing a DMA module in FPGA, this paper implemented a high-performance PCI Express system. IP Core handles the protocols defined by PCI Express...
Reconfigurable system-on-chip (RSoC) is a promising alternative to deliver both flexibility and performance at the same time, and also a technical solution looking to the future needs of embedded applications. But the complex design process is impeding the development of extensive applications. This paper proposes an RSoC design methodology based on function-level programming model on account of the...
Designs of next-generation Internet architectures propose a diverse and changing set of features in the data path of routers. These routers require high-performance programmable packet processing platforms to allow for dynamic feature deployment and adaptation. In this paper, we present programming abstractions that quantifies processing and storage of network services. We further devise a runtime...
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