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With the logic device size shrinking to 32/28nm and beyond, ultra- low k has been introduced to Cu interconnect, which makes Cu gap-fill very challenging. This paper has summarized metal hard mask, Ta(N) barrier, Cu seed and electroplating (ECP) challenges for 28nm BEOL Cu gap-fill. Metal hard mask thickness and stress greatly impact gap fill performance and need to be optimized. Thinner barrier helps...
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