The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper describes a methodology to measure process windows in-line at level using voltage contrast inspection and special families of test structures. This methodology allows rapid turn-around of experiments designed to find the most robust and best centered process conditions. Each family of structures should be laid out with a single super-pitch so that a single wafer scan can be used for one...
A test structure specifically designed to allow in-line detection of missing spacer is introduced. Missing spacer is too small to be physically detected with any current inspection tool and therefore its existence must be flagged using voltage contrast for detection with an e-beam inspection system. How this structure and methodology were used to address this defect during the ramp of a recent technology...
The ability of voltage contrast inspection to detect resistive opens and shorts was investigated. Resistive programmed defects ranging from 8 kOmega to 4 MOmega, were created using integrated poly-silicon resistors. While all the shorts were easily detected, only the 4 MOmega, open had a signal, and it was too faint for automatic detection. A model is presented to help explain these results. A follow-up...
This paper describes the technique of using electron beam inspection (EBI) for the purposes of scanning silicon-on-insulator (SOI) wafers for electrical defectivity. Using this methodology, we are able to inspect the wafer for reactive ion etch (RIE) process variation on tungsten local-interconnect levels. First, we will demonstrate that it is possible to detect electrically active defects on SOI...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.