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We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The...
Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by...
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