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This paper presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state...
This paper proposes a 1-1 MASH ΔΣ time-to-digital converter (TDC). A cascode time adder with a raised inverter threshold voltage is proposed to minimize the jitter caused by current mismatch. A differential time integrator consisting of two single-ended time integrators is proposed to minimize even-order harmonics. The detrimental effect of the nonidealities of the TDC is examined in detail. The TDC...
This paper presents a fully differential bi-directional gated delay line (BD-GDL) time integrator and its application in an all-digital first-order ΔΣ time-to-digital converter (TDC). The BD-GDL time integrator performs simultaneous time integration and multi-bit quantization, allowing rapid time integration and quantization with minimum power consumption. The nonlinearity of the BD-GDL time integrator...
This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc–dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant...
A fast-locking phase-locked loop (PLL) with variable loop dynamics is proposed. The PLL employs a time amplifier (TA) with a variable gain to amplify the phase difference between the reference clock and the output of the voltage controlled oscillator (VCO). It operates by dynamically increasing the bandwidth of the PLL during locking state to speed up locking process and decreasing the bandwidth of...
An 8-bit stage-interleaved pulse-shrinking time-to-digital converter (TDC), aiming at minimizing silicon consumption, improving the linearity to minimize the number of fine TDCs and removing the speed penalty without sacrificing conversion time and resolution is proposed. The proposed TDC quantizes time variables using a 16-stage coarse pulse-shrinking TDC with resolution 4.8 ns. The residue of the...
An area and power efficient pulse-shrinking delay-line time-to-digital converter (TDC) using a 2-step conversion scheme is presented. The proposed TDC quantizes time variables using a coarse pulse-shrinking TDC with a large per-stage time shrinkage and a fine pulse-shrinking TDC with a small per-stage time shrinkage. It offers low power and silicon consumption, and good linearity without sacrificing...
In this paper, a simple timing jitter minimization algorithm is suggested and analyzed for wireless broadband (WiBro) network. In order to reduce timing jitter which exists in delays between master and slave, next delay is estimated by using previous one. Then these estimated things are not according to exact ones which do not include jitter. But timing jitter can be certainly reduced although remaining...
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