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This paper presents a new time integrator for mixed-mode signal processing. The proposed time integrator consists of two time adders realized using a time-to-voltage and voltage-to-time conversion mechanism. All transistors of the proposed time integrator operate in an on/off mode, the time integrator is fully compatible with digital-oriented CMOS. The effect of nonidealities including charge injection,...
We propose a different method to define patterns on the Go board, which has a tengen pattern and tengen centered 9 square-patterns as well as necessary conditions for two patterns to be equivalent. Using this method, we show that our methodology can easily locate a specific or a desired pattern out of multiple games.
Existing GSG (gold sequence generator) generates only 1 bit data per clock cycle. Thus it may cause delay to the data communications. In this paper, we propose the GSG with parallel outputs for high speed data communications. Through simple matrix multiplications, we could not only derive a recursive formula in parallel form but also implement the GSG with multiple outputs. Experimental results show...
Conventional GSG (gold sequence generator) creates only 1 bit data per clock cycle. Therefore it may cause delay to the data communications. In this paper, we propose an efficient implementation method of the GSG for high speed data communications. Through simple matrix multiplications, we could not only derive a well-organized recursive formula but also implement the GSG with parallel outputs. Experimental...
Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps
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