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This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a...
In this paper, twin gate rectangular recessed channel (TG-RRC) MOSFET with independent gate control is used to realize its application in digital electronics by using it as two input logic. The input logic is controlled by the independent gates which have different work functions (Φ1 for gate 1 and Φ2 gate 2) which are separated by oxide layer of 2 nm, thus controlling various electrical parameters...
This work discusses the effectiveness of high-k dielectric as gate stack in transparent gate recessed channel (TGRC) MOSFET having 20nm gate length. The main aim of this study is to analyse the reliability issues of TGRC MOSFET in terms of analog parameters. Results indicate that with the incorporation of HfO2 as gate stack on SiO2, on-current enhances significantly whereas leakage current (off-current)...
This paper examines the reliability issues of In2O5Sn (ITO) gate electrode (Transparent Gate) Recessed Channel (TGRC) MOSFET by considering the influence of interface trap charges polarity and density present at the Si/SiO2 interface. The reliability of TGRC MOSFET is observed in terms of Linearity and distortion FOMs such as gm, gm3, VIP3. IIP3, HD3. IMD3. Results so obtained revealed that the existence...
Photo-response of solution processed flexible TIPS-pentacene organic field-effect transistors is evaluated under illumination with visible light of red, green, and blue colors having minimum wavelengths of 620, 520, and 460 nm. For −10 V operation, pristine photo-OFETs exhibited average field-effect mobility of 0.11 cm$^{2}\text{V}^{-1}\text{s}^{-1}$ , near zero threshold voltage, and current ON–OFF...
This paper presents a comparative study of dual material double gate junctionless transistor with the single material double gate junctionless transistor. A review of the basic modelling of the Junctionless transistor is also given in the paper. The surface potential of both structures are compared. The threshold voltage compared for both the devices shows that the single material gate has higher...
The use of nonlinear loads and power electronics switches are increasing day by day and causing so many problems like, harmonics pollution, reactive power demand, low power factor etc. These problems are mitigated through Shunt Active Power Filter (SAPF) but the system robustness is depending on the control algorithm. In this article the Modified P-Q theory is implemented to mitigate power quality...
As day by day continuing research in the field of nanotechnology, the CMOS manufacturing process scaled down in nano-dimensions at the cost of severe process variations and high leakage current which resulting large power dissipation. Therefore the leakage current and power dissipation becomes increasingly more focused in VLSI circuit design. Carbon NanoTube Field Effect Transistor (CNFETs) is suited...
With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. Over the years, adiabatic circuit designs have been studied and found to be effective in achieving low power in VLSI circuits. This paper briefs some of the adiabatic logic families such as ECRL, 2N-2N2P and PFAL. And...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
A low loss wideband (1–7GHz) SPDT switch using 0.13µm GaAs/InAlAs MHEMT MMIC process is designed, fabricated and tested both on-wafer and in test fixture. The measured results are in close agreement with specifications and simulations, which exhibit insertion loss of 1.05 ±0.05dB, with isolation of 28dB, minimum. All three ports of this SPDT switch are well matched having return loss of more than...
Dynamic domino logic circuits are used for high system performance. The dynamic circuits offer superior speed and power dissipation over static CMOS circuits. But these circuits suffer from limitations such as charge leakage, noise and charge sharing. This article provides analysis of the different keeper topologies on pseudo domino logic circuits with reference to power dissipation. The circuit simulations...
In this paper, basically the delay and the noise margin parameter associated in the circuit has been analyzed. The paper gives a better approach for the reduction in delay variation and compares the result with different-different types of domino logic circuits. The other domino logic circuits used to discriminate the result of proposed circuit are footed domino logic circuit, footless domino logic...
The progress towards making efficient chips, in terms of area, speed and power continues to remain a major concern of every silicon industry. The various effects that become prominent at nanometer level hinders this progress. This is a paper that looks into: scaling, its effects (short-channel effects, as it is called) and compares scaled single gate and scaled multiple gate FETs on important properties...
ZrO2/Si thin films were fabricated using sputtering technique and the deposited films were annealed at temperatures of 873 K and 1073 K. From HRTEM analysis, it is observed that the as-deposited ZrO2 layers are partly amorphous and fully crystallize after post-deposition annealed at 1073 K. The dielectric constant of the as-deposited films was 15.0 and it increased to 29.0 with increase of annealing...
As the nano scale device performance depends on the detailed engineering of the dopant distribution, advanced doping processes are required. Progressing towards 3D-structures like FinFETs, studying the dopant gate overlap and conformality of doping calls for metrology with 3D-resolution and the ability to confine the analyzed volume to a small 3D-structure. We demonstrate that through an appropriate...
Junction strategies for FINFETs and high mobility channel devices in 1x nm node are discussed. Doping conformality and doping damage control are the keys for high performance scaled FINFETs. Damage-less conformal fin doping can be provided by Self Regulatory Plasma Doping (SRPD) process, based on radical absorption in low energy plasma and subsequent drive-in anneal. SRPD demonstrates 20% Ion gain...
Weights Binary Decision Diagram (WBDD) based timing analysis of combinational circuit is proposed. Here we express the combinational circuit as a directed graph. We compute and store the delay of combinational circuits for all combination of inputs for the range of delay values based on controlling values. Hence it is possible to look up the built in library and calculate the output delay of any combinational...
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