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Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface...
In this paper, we investigate reliability testing for a glass interposer. The test vehicle is an assembled glass interposer with a chip, a BT substrate. The structure of a glass interposer with two redistribution layers (RDLs) on the front-side and one RDL on the back-side has been evaluated and developed. Key technologies, including via fabrication, front-side RDL formation, microbumping, temporary...
In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass...
This paper describes a handling process for a thin glass panel, 200 mm × 200 mm × 130 (im, through double-side redistribution layer (RDL) formation to enable cost-effective fabrication of through-glass-via (TGV) interposers. The integration scheme includes lamination of a low-temperature bonding material utilizing a lamination process temperature of less than 100°C to bond a thin (130-μm) glass panel...
In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, glass thinning and backside RDL formation, were developed and integrated to perform well...
With the increase of data rate, signal integrity (SI) becomes a bigger challenge for printed circuit board (PCB) designs. Power noise as well as signal loss, inter-symbol interference (ISI), crosstalk needs to be taken into account to ensure a good quality signal design. In this paper, a design case is shared where power noise greatly impacts SATA performance and leads to hard disk (HDD) disconnection...
In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent...
KLauS is an ASIC produced in the AMS 0.35µm SiGe technology to read out the charge signals from silicon photomultipliers. Developed as an analog front end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is supposed to measure the charge signal of the sensors in a large dynamic range and with a high precision. In order to compensate...
The charge accumulation on the surface of dielectric materials is a long-term academic research focus. As part of an effort to understand the origins of this behavior, surface charge distribution on silicon rubber under DC high voltage before and after flashover in atmosphere was measured by an electrostatic voltmeter with a vibrating Kelvin probe. Three types of electrode systems were employed in...
Empowered by rapid advance of high performance computer architectures and software, it is now possible for scientists to perform high resolution simulations with unprecedented accuracy. Nowadays, the total size of data from a large-scale simulation can easily exceed hundreds of terabytes or even petabytes, distributed over a large number of time steps. The sheer size of data makes it difficult to...
In this paper we design a high-sensitivity DVB-T (digital video broadcasting-terrestrial) system using dual receivers and silicon tuners. We have modified and utilized two receivers in our front end, each integrated with a tuner by using an OFDM (orthogonal frequency division multiplexing) structure to demodulate the receiving signal. Dual receivers compensate each other and improve the sensitivity...
With electronic package tends to be lighter, thinner and smaller, the design of multi-chip become more and more popular. Howev'er, multi-chip in a package also represents multiple heat sources that will result in high thermal dissipation and new technology is required to remove the heat effectively. The 3D stacked package with Through Silicon Via (TSV) technology is developed for chip to chip stacking...
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