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Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. We construct minimum logic networks of guaranteed single soft error resilience by combining error detection and clock gating, and leveraging an existing fault-secure logic design technique, which is to construct group-sliced logic networks with...
Successful fabrication of a variety of nanoscale devices leads to research on nanoscale device integration, nano-architecture exploration, and nanoelectronic design techniques. This paper proposes a complete set of linear complexity catastrophic defect mapping techniques for CNT crossbar nano-architecture, as well as an adaptive CNT matching method for double gate CN-FETs in the presence of CNT misalignment...
An outstanding challenge for realizing nanoelectronic systems is nano-interface design, i.e., how to precisely access a nanoscale wire in an array for communication between a nanoscale system and the outside world. Existing nanoelectronic addressing methods are based on implementation of binary decoders, which requires unrealistic precise layout design in nanotechnology. In this paper, I propose voltage...
Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. However, no nanoelectronic architecture has been proposed which is solely based on carbon nanotubes and carbon nanotube field effect transistors. The reasons include lack of a self-assembly technology...
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