The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper proposes a distributed and scalable hardware solution for efficient barrier synchronization management on many-core Network-on-Chips (NoCs). It includes two hardware modules, named Root Distributed and Scalable Barrier Synchronizer (Root DSBS) and Leaf Distributed and Scalable Barrier Synchronizer (Leaf DSBS). The Root DSBS is located in the central node, connecting to the processor core...
In this paper, we propose a fast barrier synchronization mechanism, targeting Network-on-Chip based many-core architectures. Its salient feature is that, once the barrier condition is reached, the “barrier release” acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization...
Parallelized shared variable applications running on multi-core Network-on-Chips (NoCs) require efficient support for synchronization, since communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. In this paper, we propose a dedicated hardware module for synchronization management. This module is called Synchronization...
This paper explores a dynamic buffer allocation technique to guide a distributed synchronization architecture to support efficient synchronization on multi-core Network-on-Chips (NoCs). The synchronization architecture features two physical buffers to be able to concurrently queue and handle synchronization requests issued by the local processor and remote processors via the on-chip network. Using...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.