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We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The...
This paper presents an efficient design method to construct a flexible, high band-width, and multi-wordlength multiplier. The method includes a new sticky Booth coding technique to tackle the unscalability problem in traditional Booth coding for multi-wordlength multiplier design. Moreover, a cell array based architecture is developed for efficient implementation of the multiplier, which can be conveniently...
SIMD architectures, comprising of both scalar and parallel units, have been widely used in media processors. To further improve the performance, much effort has been made to enhance the design of both units, while little attention has been placed on the relationship between the units. This paper demonstrates that a dynamic coupling mechanism, which can dynamically transform the scalar and parallel...
To further improve the performance of SIMD (Single Instruction Multiple Data) architectures, which are widely used in the wireless communication domain. The main components of Long Term Evolution (LTE) protocol are analyzed. Performance investigation is taken on a cycle-accurate simulator, featuring the main characteristics of existing SIMD architectures. Based on the investigation, three insightful...
Hybrid architectures combined of VLIW, SIMD and multi-core schemes are increasingly prevailing in media processors, due to the abundant parallelism existed in media applications. However, parameters for current combinations such as the VLIW length, SIMD width and core count are set mainly according to simple profiling or the designer's experience rather than a systematic and in-depth investigation...
SIMD architectures are less efficient for applications with the diverse control-flow behavior, which can be mainly attributed to the requirement of the identical control-flow. In this paper, we propose a novel instruction shuffle scheme that features an efficient control-flow handling mechanism. The cornerstones are composed of a shuffle source instruction buffer array and an instruction shuffle unit...
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