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An 8-bit stage-interleaved pulse-shrinking time-to-digital converter (TDC), aiming at minimizing silicon consumption, improving the linearity to minimize the number of fine TDCs and removing the speed penalty without sacrificing conversion time and resolution is proposed. The proposed TDC quantizes time variables using a 16-stage coarse pulse-shrinking TDC with resolution 4.8 ns. The residue of the...
An area and power efficient pulse-shrinking delay-line time-to-digital converter (TDC) using a 2-step conversion scheme is presented. The proposed TDC quantizes time variables using a coarse pulse-shrinking TDC with a large per-stage time shrinkage and a fine pulse-shrinking TDC with a small per-stage time shrinkage. It offers low power and silicon consumption, and good linearity without sacrificing...
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