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This paper proposes a 3D stacked buck converter with a 15μm thick spiral inductor on a silicon Interposer, which is suitable for fine-grain power-supply voltage control in SiP's. Our newly developed silicon interposer technology realizes a fine-pitch design rule (Line/Space=20μm/20μm, via hole diameter =30um) at the metal thickness of 15μm as well as conventional interposers with 5μm metal thickness...
The fastest ever 4.2 Gbps 3D-Solid State Drive (SSD) with multi-level cell (MLC) NAND flash memories is proposed. The proposed NAND channel number detector automatically detects the number of channels, that is, the number of NAND chips written at the same time. Based on the number of channels, the intelligent program-voltage booster adaptively optimizes the switching clock. As a result, the proposed...
A novel Switched Resonant Clocking (SRC) scheme is proposed to solve two basic problems of the conventional resonant clocking, that is, power increase and clock waveform inability at the lower clock frequency region. The power increase prohibits widely-used dynamic frequency scaling (DFS) and the waveform instability hinders low-speed function tests. A test chip in 0.18 mum CMOS is manufactured and...
A low-power program-voltage generator (PVG) using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller is implemented. SSD consists of the HVMOS chip (0.35 x 0.50 mm2), the AFD controller chip (0.67 x 0.28mm2), a 270nH 0.5Omega inductor in an interposer (5 x 5mm2), and a 56 nm 16 Gb NAND Flash memory chip.
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