Search results for: Abhijit Biswas

Items from 1 to 20 out of 95 results

article

Non‐Linear Optics at Twist Interfaces in h‐BN/SiC Heterostructures

Abhijit Biswas, Rui Xu, Gustavo A. Alvarez, Jin Zhang, more

Advanced Materials > 35 > 47 > n/a - n/a

Understanding the emergent electronic structure in twisted atomically thin layers has led to the exciting field of twistronics. However, practical applications of such systems are challenging since the specific angular correlations between the layers must be precisely controlled and the layers have to be single crystalline with uniform atomic ordering. Here, an alternative, simple, and scalable approach...

article

Special Issue on the 3rd International Conference Microelectronics, Circuits and Systems (Micro 2016)

Jyotsna Kumar Mandal, Abhijit Biswas, Dulal Acharjee

Microsystem Technologies > 2019 > 25 > 5 > 1525-1525

article

Analytical model of nanoscale junctionless transistors towards controlling of short channel effects through source/drain underlap and channel thickness engineering

Debapriya Roy, Abhijit Biswas

Superlattices and Microstructures > 2018 > 113 > C > 71-81

We develop a 2D analytical subthreshold model for nanoscale double-gate junctionless transistors (DGJLTs) with gate-source/drain underlap. The model is validated using well-calibrated TCAD simulation deck obtained by comparing experimental data in the literature. To analyze and control short-channel effects, we calculate the threshold voltage, drain induced barrier lowering (DIBL) and subthreshold...

article

Correlating tribological performance with phase transformation behavior for electroless Ni-(high)P coating

Abhijit Biswas, Suman Kalyan Das, Prasanta Sahoo

Surface and Coatings Technology > 2017 > 328 > C > 102-114

The present study attempts to systematically assess the effect of varying the heat treatment temperature together with the duration of heat treatment on the tribological performance of EN coating and also correlating the same with the microstructural observations. High phosphorous nickel coating is developed in-house over steel substrates. The coatings are subjected to heat treatment at temperatures...

article

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

Debapriya Roy, Abhijit Biswas

Superlattices and Microstructures > 2017 > 110 > C > 114-125

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length L_ED of 10 nm and source-side spacer length L_ES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain...

article

Improved performance of InGaN/GaN MQW LEDs with trapezoidal wells and gradually thinned barrier layers towards anode

Himanshu Karan, Abhijit Biswas, Mainak Saha

Optics Communications > 2017 > 400 > C > 89-95

We design and evaluate the performance of three InGaN/GaN multiple quantum well blue LEDs – A. rectangular quantum wells with a fixed barrier width, B. trapezoidal quantum wells with a fixed barrier width, and C. trapezoidal quantum wells with a decreasing barrier width towards the anode end – in terms of efficiency droop and power output. We obtain band diagram, electric field, emission spectra and...

article

Impact of channel thickness and spacer length on logic performance of p-Ge/n-Si hybrid CMOSFETs for ULSI applications

Suchismita De, Suchismita Tewari, Abhijit Biswas, Abhijit Mallik

Superlattices and Microstructures > 2017 > 109 > Complete > 316-323

We investigate the logic performance of hybrid (H) CMOS devices comprising Ge p-MOSFETs and Si n-MOSFETs in terms of rise time, fall time, propagation delay and noise margins using extensive numerical device simulation. We analyse CMOS devices featuring channel thickness (T_ch) ranging 5–10 nm, spacer length (L_sp) from 1 to 10 nm at channel length (L_g) of both 20 and 30 nm. Our investigation reveals...

article

Toward Self-Similar Propagation of Optical Pulses in a Dispersion Tailored, Nonlinear, and Segmented Bragg-Fiber at 2.8 $\mu$m

Piyali Biswas, Bishnu Pada Pal, Abhijit Biswas, Somnath Ghosh

IEEE Photonics Journal > 2017 > 9 > 4 > 1 - 12

We demonstrate self-similar stable propagation of parabolic optical pulses through a highly nonlinear specialty Bragg fiber at 2.8

$\mu$

m by a numerical approach. To obtain such propagation characteristics over a longer length of a Bragg fiber, we propose and verify a fiber design scheme that underpins passive introduction of a rapidly varying group-velocity dispersion around its zero dispersion wavelength...

article

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Chandrima Mondal, Abhijit Biswas

Materials Science in Semiconductor Processing > 2017 > 66 > C > 109-116

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20nm with channel thickness values of 10 and 5nm. Our results reveal that 10nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off...

article

Development of noise model for InAsSb MOSFETs and their application in low noise amplifiers

Swagata Bhattacherjee, Abhijit Biswas

Microsystem Technologies > 2019 > 25 > 5 > 1555-1562

In this paper, we develop the low frequency noise (LFN) model for symmetric double gate InAsSb channel n-MOSFETs and report noise performance of such devices as well as amplifier circuits built using them. Our noise model relies on the drain current I_d which is obtained from the carrier concentration and Pao-Sah’s current formulation taking into account field dependent electron mobility and interface...

article

Synthesis of nano-textured polystyrene/ZnO coatings with excellent transparency and superhydrophobicity

Amrita Hooda, M.S. Goyat, Rajeev Gupta, Manish Prateek, more

Materials Chemistry and Physics > 2017 > 193 > C > 447-452

Transparent superhydrophobic polystyrene/ZnO nanocoating, possessing an average roughness of 28 nm and high contact angle (>150°) has been synthesized through a modified facile sol–gel route. The anticipated hierarchical roughness of the coating was obtained using dual functionalized ZnO nanoparticles. Chlorotrimethylsilane and 3-mercaptopropyltrimethoxy silane were espoused as nanoparticle surface...

article

Growth and engineering of perovskite SrIrO3 thin films

Abhijit Biswas, Yoon H. Jeong

Current Applied Physics > 2017 > 17 > 5 > 605-614

5d transition-metal-based oxides display emergent phenomena due to the competition between the relevant energy scales of the correlation, bandwidth, and most importantly, the strong spin-orbit coupling (SOC). Starting from the prediction of novel oxide topological insulators in bilayer ABO₃ (B = 5d elements) thin-film grown along the (111) direction, 5d-based perovskites (Pv) form a new paradigm in...

article

Atomically flat single terminated oxide substrate surfaces

Abhijit Biswas, Chan-Ho Yang, Ramamoorthy Ramesh, Yoon H. Jeong

Progress in Surface Science > 2017 > 92 > 2 > 117-141

Scientific interest in atomically controlled layer-by-layer fabrication of transition metal oxide thin films and heterostructures has increased intensely in recent decades for basic physics reasons as well as for technological applications. This trend has to do, in part, with the coming post-Moore era, and functional oxide electronics could be regarded as a viable alternative for the current semiconductor...

article

Can attempts to delight customers with surprise gains boomerang? A test using low-price guarantees

Sujay Dutta, Abhijit Guha, Abhijit Biswas, Dhruv Grewal

Journal of the Academy of Marketing Science > 2019 > 47 > 3 > 417-437

Despite cautionary advice against it, delighting consumers by offering them pleasant surprises is widely advocated. In this paper, using a low-price guarantee context, we show that retailers’ attempts to use surprise gains to delight consumers might lead to subpar outcomes, if a countervailing cognition such as suspicion of retailer opportunism dominates consumers’ thinking. In a low-price guarantee,...

chapter

An improved congestion free modified fat tree Network — On — Chip Topology

Abhijit Biswas, Md. Anwar Hussain, Alakesh Kalita

2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES) > 759 - 763

2016 International conference on Signal Processing, Communication, Power and Embedded System (SCOPES)

As the current decade is witnessing a shift from traditional System — On — Chip (SoC) to Network — On — Chip, but the inherent problems such as congestion, latency and delay still remains the major issues of concern. The effect of these issues in a chip may somehow be minimized by carefully designing a topology and a suitable routing algorithm which offers both path diversity and scalability. In this...

article

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Debapriya Roy, Abhijit Biswas

Superlattices and Microstructures > 2016 > 97 > C > 140-154

Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate...

article

Investigating the Pleasures of Sin: The Contingent Role of Arousal‐Seeking Disposition in Consumers' Evaluations of Vice and Virtue Product Offerings

Swati Verma, Abhijit Guha, Abhijit Biswas

Psychology & Marketing > 33 > 8 > 620 - 628

Mixed bundles of vice and virtue are an increasingly important product category. However, many mixed bundles fail in the marketplace, and so it is important to examine how consumers evaluate such mixed bundles. This paper examines consumers' affective responses and consequent purchase evaluations for a mixed vice‐virtue bundle versus a pure vice product. Results of Study 1 show that purchase intentions...

article

Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors

Debapriya Roy, Abhijit Biswas

Microsystem Technologies > 2017 > 23 > 7 > 2847-2857

We investigate the impact of sidewall spacers on the analog/RF performance of double gate junctionless transistors at channel length of 30 nm using extensive numerical device simulation. Furthermore, we report the performance of a common source amplifier built employing such devices. The simulation deck is calibrated with experimental results published elsewhere. The influence of spacer layers is...

article

Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs

Suchismita Tewari, Abhijit Biswas, Abhijit Mallik

IEEE Transactions on Electron Devices > 2016 > 63 > 6 > 2313 - 2320

An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In_0.75Ga_0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths (

$L_{g}$

) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental...

chapter

A limited scalable MIN FAT TREE topology based on fully grouped routing strategy for network — On — Chip

Abhijit Biswas, Md. Anwar Hussain

2016 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT) > 690 - 694

2016 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

The efficiency of a System — On — Chip (SoC) depends upon the arrangement of different components on the chip. In order to get full operational capability, the communication between these components must incur less cost: latency and delay. Traditionally these components are connected via shared bus, which becomes a bottleneck. To overcome this bottleneck a new era has begun called the Network — on...

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LOGIC GATES (9)
MOSFET (7)
NUMERICAL RELATIVITY (7)
ROUTING (7)
TOPOLOGY (7)
SILICON (6)
FAT TREE (5)
INDIUM GALLIUM ARSENIDE (5)
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RELATIVISTIC PRECESSION (5)
4.25.DM (4)
4.90.+E (4)
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NOC (4)
PORTS (COMPUTERS) (4)
SCALABILITY (4)
SUBTHRESHOLD SLOPE (4)
TCAD (4)
THRESHOLD VOLTAGE (4)
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EARTH (3)
FATS (3)
GAIN (3)
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MOSFETS (3)
NANOPARTICLES (3)
NUMERICAL MODELS (3)
PERFORMANCE EVALUATION (3)
PERIHELION PRECESSION (3)
RELATIVITY THEORY (3)
TRANSCONDUCTANCE (3)
VENUS (3)
95.10.CE (2)
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ANALOG CIRCUITS (2)
ANOMALOUS PERIHELION PRECESSION (2)
BIOLOGICAL SYSTEM MODELING (2)
BIOMECHANICS (2)
CATALYSIS (2)
CMOS INTEGRATED CIRCUITS (2)
CUT-OFF FREQUENCY (2)
DELAY (2)
DELAYS (2)
DOPING (2)
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HARDWARE (2)
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INGAAS MOSFET (2)
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PERFOMANCE (2)
PROPAGATION DELAY (2)
RECEPTOR POTENTIAL (2)
RELATIVISTIC DEFLECTION (2)
RELIABILITY (2)
SEMICONDUCTOR DEVICE MODELING (2)
SIGNAL DEFAULT (2)
SOC (2)
SPACE VEHICLES (2)
SWITCH (2)
SYSTEM-ON-CHIP (2)
TIME DELAY (2)
TOPLOLOGY (2)
UNITY GAIN CUT-OFF FREQUENCY (2)
2-D COMPACT MODEL (1)
5D-BASED OXIDES (1)
ABSORPTION (1)
ADAPTIVE RELAXATION PULSE FREQUENCY MODULATION (1)
ADAPTIVE ROUTING ALGORITHM (1)
AGE CONGRUENCY (1)
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ANALOG CIRCUIT APPLICATIONS (1)
ANALOG FIGURES OF MERIT (1)
ANALOG PERFORMANCE (1)
ANALOG/RADIO FREQUENCY (1)
ANALYTICAL MODELS (1)
APPROXIMATION METHODS (1)
APSYS SIMULATION (1)
ASYMMETRIC INP/INGAAS NMOSFET (1)
ASYMMETRIC UNDERLAP SPACER (1)
ATOMIC FLATNESS (1)
ATOMICALLY CONTROLLED THIN FILMS (1)
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INFONA - science communication portal

Search results for: Abhijit Biswas

Non‐Linear Optics at Twist Interfaces in h‐BN/SiC Heterostructures

Special Issue on the 3rd International Conference Microelectronics, Circuits and Systems (Micro 2016)

Analytical model of nanoscale junctionless transistors towards controlling of short channel effects through source/drain underlap and channel thickness engineering

Correlating tribological performance with phase transformation behavior for electroless Ni-(high)P coating

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

Improved performance of InGaN/GaN MQW LEDs with trapezoidal wells and gradually thinned barrier layers towards anode

Impact of channel thickness and spacer length on logic performance of p-Ge/n-Si hybrid CMOSFETs for ULSI applications

Toward Self-Similar Propagation of Optical Pulses in a Dispersion Tailored, Nonlinear, and Segmented Bragg-Fiber at 2.8 $\mu$m

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Development of noise model for InAsSb MOSFETs and their application in low noise amplifiers

Synthesis of nano-textured polystyrene/ZnO coatings with excellent transparency and superhydrophobicity

Growth and engineering of perovskite SrIrO3 thin films

Atomically flat single terminated oxide substrate surfaces

Can attempts to delight customers with surprise gains boomerang? A test using low-price guarantees

An improved congestion free modified fat tree Network — On — Chip Topology

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Investigating the Pleasures of Sin: The Contingent Role of Arousal‐Seeking Disposition in Consumers' Evaluations of Vice and Virtue Product Offerings

Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors

Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs

A limited scalable MIN FAT TREE topology based on fully grouped routing strategy for network — On — Chip

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