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Solid-phase epitaxy combined with Ge implantation has been employed to process silicon wafer. The resulting microstructural details have been examined by high-resolution transmission electron microscopy. It is observed that a thin layer of SiGe alloy forms around the projected ion range. Some dislocations as half loops extend into the substrate itself instead of the top part above the alloy layer,...
Using a semi-empirical, sp3d5s* tight-binding approach and a 'top-of-the-barrier' ballistic FET model, we report full-band simulations of ballistic Si and Ge nanowire FETs with various channel orientations and wire diameters. We find that the nanowire FET performance displays a strong orientation and diameter dependence, and [110] is the optimum orientation for both Si and Ge nanowire FETs
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