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This paper presents a 5.2–5.7GHz low voltage sub-sampling phase locked loop (LV-SSPLL). It adopts a new low voltage multi-modulus frequency divider (LVMMD) based on Extended True Single-Phase Clock (ETSPC) and TSPC Logic, which can operates at 7 GHz frequency under only 1V supply voltage in 0.18 μm CMOS process. All the blocks of LV-SSPLL excluding the output buffer operate at 1V supply voltage. The...
In this paper a 1-V supply, 15-bit ADC design for audio applications is presented. The second order CIFB modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification...
This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference...
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