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This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap...
This paper presents a new capacitor array architecture to achieve a 6 bit 550Ms/s energy-efficient SAR with 65nm CMOS, which also takes up smaller area than traditional SAR. The bypass logic is a key feature to speed up the SA algorithm. Dynamic logic is used in the critical path to accelerate the speed. The whole circuit is supplied with 1.2V voltage. Simulation results show that the SAR achieves...
A relatively low-power 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the typical structure of SAR ADC, some effective techniques including bootstrapped sampling-switch used to suppress nonlinear distortion, dynamic comparator to reduce power dissipation and the offset-calibration to ensure conversion accuracy have been employed...
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology...
A nanopower subthreshold bandgap reference with 30ppm/°C from −30°C to 150°C has been implemented in 0.18µm CMOS. This design is based on weighted ΔVGS and is free of resistors. The major advantage of this design is that with nanopower consumption, the temperature range is extremely wide. To achieve high performance of subthreshold bandgap operating in high temperature (above 80°C), a leakage current...
This paper presents a high precision multi-bit audio ΔΣ modulator working under IV supply. We propose a kind of asynchronous 4-bit successive approximation quantizer without fast clock generation. Feed-forward topology with digital summing is adopted to relax the amplifier design requirement. Power efficient single stage OTA is adopted to drive the large sampling capacitor with...
A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
A low power voltage reference is implemented in a standard 0.18 μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in...
A 15-bit 3rd order ΔΣ modulator is presented. The feed forward topology with 18-level quantizer is adopted. The signal swing of the 1st integrator is effectively suppressed. A current-mirror OTA with 42dB DC gain is used in the 1st integrator. Chop stabilization is employed to remove the flicker noise. The prototype is fabricated in 0.18μm CMOS. The active die area is 0.85×0.85mm2. The power consumption...
A 1.1 mW 87 dB dynamic range 3rd order ΔΣ modulator is implemented in 0.18 μm CMOS technology for the audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed and only one simple current mirror single-stage OTA with 34 dB DC gain is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB...
A multi-standard transceiver requires a wide-band radio frequency front-end in order to process RF signals of any frequency included by all the standards concerned. A noise cancellation technology is utilized in the low noise amplifier (LNA) to cancel the noise introduced by the source resistance matching segment. An active balun is embedded in the input stage of the mixer, which connect the single-end...
In this paper, a low voltage bandgap reference with high precision is presented. Utilizing current mode structure, the minimum voltage of the proposed bandgap circuit can be reduced to 900 mV. Compensated with VEB linearization technique, this bandgap reference can reach a temperature coefficient of 10 ppm/degC in the range from 0degC to 150degC. With 1.1-V supply voltage, the power is 47 uW and the...
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