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In this paper a novel design of 4-bit 10GS/s ADC is presented. The ADC is designed in 180-nm CMOS process with the aid of behavior models. In the design of ADC, we combine double-sampling with time-interleaved approaches for the first time. Because of the use of the behavior models, we can stimulate the whole ADC before the system is completed implemented, which make us evaluate the finished modules...
A novel full differential double sampling circuit is presented in the paper. The traditional full differential single sampling circuit is compared with the proposed full differential double sampling one to show that the latter has more efficiency and higher speed The proposed full differential double sampling circuit is designed in TSMC 0.18μm CMOS process technology. The simulation results show that...
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