In this paper a novel design of 4-bit 10GS/s ADC is presented. The ADC is designed in 180-nm CMOS process with the aid of behavior models. In the design of ADC, we combine double-sampling with time-interleaved approaches for the first time. Because of the use of the behavior models, we can stimulate the whole ADC before the system is completed implemented, which make us evaluate the finished modules even at the transistor level. The simulation results show that the designed ADC can work well at 10GSps and has a SFDR of 37.6 dB.