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The authors would like to point out the following correction in the total power consumptions recorded in Table IV of the published article <xref ref-type="bibr" rid="ref1">[1]</xref>. The total power consumptions of the proposed design and the design <xref ref-type="bibr" rid="ref2">[2]</xref> in comparison should be corrected as shown...
At present, many Beidou tracking stations over the world have been set up for international GNSS Monitoring and Assessment System (iGMAS) and a pilot project named Multi-GNSS Experiment (MGEX) is implemented. Each station was equipped with the Multi-GNSS receivers which are able to track BeiDou as well as GPS signals. Furthermore some of stations were equipped with high-precision atomic clocks as...
With the globalization of integrated circuit (IC) design and fabrication, there is a growing concern on the devastating impact of subverted chip supply. This paper presents a current sensing circuit that converts the current activity on local power grid to a timing pulse to detect if an IC is Trojan-infected. This new approach increases the Trojan detection sensitivity by combining the switching activity...
This paper presents a new methodology of multiplierless implementation of inner-product computation. The inner-product computation is decomposed to form an architecture that facilitates an efficient serial accumulation of the 1's in the partial product matrix of each multiplication of a pair of elements from the input vectors. The 1's that appear at each partial product position are accumulated by...
This paper presents a new approach to serial/parallel multiplier design by using parallel 1psilas counters to accumulate the binary partial product bits. The 1psilas in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to [log2 N]+1. This logarithmic reduction results...
A nonlinear sine-weighted digital-to-analog converter (DAC) can significantly reduces the power consumption and the complexity of direct digital frequency synthesizers (DDFSs). With the sine conversion implemented in the DAC, the phase-to-amplitude mapping (PAM) stage can be totally eliminated, thus drastically reduces the latency and increases the speed of the DDFS as the PAM stage is usually the...
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