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In this paper a compact model both for bipolar and unipolar resistive switching device is proposed. Basic I-V characteristics of RRAM are easily and correctly represented by this model. The model is verified by the bipolar RRAM experiment results. The model can be used as simple and fast tool to design and optimize RRAM.
Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an...
Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically...
Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically...
In this paper, we propose a closed form method to evaluate the read stability of an SRAM cell via quartic root finding. By utilizing a simplified MOSFET device model, we model SRAM cell stability by a system of quartic equations. The algebraic nature of the equations along with simplified region boundaries provide the insight that only a few combinations of device operating regions correspond to the...
A new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both I-V and C-V characteristics of a transistor, finite data points are identified by their physical meaning; the impact of process and design variations is embedded into these points as closed-form expressions. Then, the entire I-V and C-V are extrapolated using polynomial...
Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the difference between the nominal and perturbed circuit waveforms by calculating the moments in frequency-domain via efficient iterative method. The algorithm can be used to accurately reproduce the differential waveforms, or...
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