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A 9.95 to 11.1 Gb/s transceiver in 0.13mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL to exceed SONET jitter specifications. A half-rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 9.5 inches of FR4 is equalized resulting in random jitter(rms) under 4mUI. Power consumption is 800mW
A continuous-rate CDR (clock and data recovery) circuit is presented that operates from 12.5 Mb/s to 2.7 Gb/s. The circuit automatically detects a change in input data rate, acquires the new frequency and reports the data rate to the user without the need for an external reference clock or any programming. In tracking mode, it uses a dual-loop DLL/PLL to exceed the SONET jitter specifications.
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