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We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The Lg = 500 nm...
We demonstrate key factors enabling mobility improvement at both low charge density and high density (>5 × 1012/cm2) in In0.7Ga0.3As quantum-well MOSFETs. We further show sub-threshold swing (SS) and on-current (Id) improvement in tunneling FETs (TFETs). By reducing EOT, optimizing the top-barrier/high-κ interface, and confining carriers in In0.7Ga0.3As channel using In0.52Al0.48As bottom-barrier,...
The performance and reliability of ZrO2/In0.53Ga0.47As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlOx interlayer at the ZrO2/In0.53Ga0.47As interface is a key to reduce border traps, interface traps and move ZrO2 fixed charge away from the In0.53Ga0.47As. Border traps are reduced ~3x, effective fixed charges are reduced ~3x and...
Although III-V semiconductors have intrinsically higher electron mobility compared to Si, a high-quality gate stack with low Dit is still required to realize III-V surface channel MOSFETs. Recently, significant effort has been focused on improving high-k/III-V interfaces using different interfacial passivation layers (IPL) and surface passivation techniques. These include MBE deposition of Ga2O3(Gd...
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