The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 0.5-V BJT-based thermal sensor design is first demonstrated in a 10-nm CMOS. A charge-pump technique is proposed for operating with a digital core supply voltage as low as 0.5 V without the restriction on forward junction bias (∼0.7V). A switched-capacitor integrator loop is presented for process-insensitive voltage-to-frequency conversion. This thermal sensor achieves an RMS resolution of ±0.173°C,...
In recent years, the development of technologies and medical devices has made the birth rate and mortality decline and this leads to the widespread phenomenon of global aging and the trend of aged society. Through the continuous verification by the collection of daily data and with the help of recording the physiological state, patients receive more accurate treatments. The heart rate variability...
A novel method for fault location is proposed in this paper, which is based on fault voltages and currents sampled synchronously on both ends of the fault line. This algorithm is based on precise integration. Using the synchronous measurement data at the ends of the fault line, it computes the voltage along transmission line. Then comparing two groups of voltage, it can find out the location of trouble...
A novel three-dimensional (3D) NAND structure containing both vertical gate (VG) framework and gate-all-around (GAA) cell structure is innovated and demonstrated. It is fabricated on alternating layers of silicon dioxide (OX) and polysilicon (PL) by using 43nm technology. To our knowledge, one of the major advantages of the novel structure is the smaller cell unit footprint than vertical channel (VC)...
Severe and unexpected yield loss (∼26% in avg.) is found in the early development stage of the advanced flash memory. The major failure mode, array bridging contact, is revealed as the root cause and mainly induced by undercutting photo-resist (PR) profile. In this work, a novel scheme, anti-etch bottom anti-reflective coating (anti-etch BARC), is used instead of the conventional dual ARC (BARC/dielectric...
High-data-rate wireless technologies such as HSUPA and LTE are power-hungry because of the fundamental correlation between data rate and transmit power. Furthermore, the high peak-to-average power ratio (PAPR) of the modulated signals causes a degradation in PA efficiency, since the supply voltage of the PA must be high enough to provide the peak output voltage without loss of linearity. Envelope...
This paper proposes a systematic innovation approach by integrating the function analysis and trimming method into the conceptual design activities of new product development (NPD). Concept design is considered to be one of the pivotal phases in NPD process which has a significant impact on downstream NPD activities such as ideas selection and detail design. Despite the recognized importance of concept...
This paper presents a complementary metal-oxide-semiconductor (CMOS) compatible urea enzyme field effect transistor (FET) without enzyme immobilization. The natural formed aluminum oxide (Al2O3) above the top metal is used as the hydrogen sensing membrane. All the devices were fabricated by TSMC 0.35μm 2P4M CMOS process. In order to realize the micro sensing biological sensing system, the traditional...
In this paper, a calculable dipole antenna is introduced into the conventional standard site method (SSM) to overcome the problem caused by the variation in the antenna factors for an antenna located at different heights above a conducting ground plane and to improve the accuracy of the antenna measurement. The variation of antenna factors at different heights is calculated and adopted in the antenna...
The advent of worldwide deregulation of power industry and unbundling of transmission services have resulted in the need to measure the flow of power primarily for pricing and tariff purposes. Reliable analysis and prediction of electrical losses is therefore attracting more attention than ever for efficient power system management. This paper presents a novel approach for the loss prediction in the...
This article mainly focuses on two treatment methods in FIR model identification for the abnormality in measured data set. One is called linear interpolation method(LIM), whose essence is to rebuild the data set according to linear interpolation after indicating the abnormal data. The other is the method of identification based on segments of data(ISDM). The idea is to remove the abnormal data and...
The idea screening of a new product concept is perhaps the most critical activity in new product development (NPD). This paper presents a fuzzy synthetic evaluation method (FSEM) for selecting an optimum design alternatives based on fuzzy set theory. The process involves constructing a hierarchical objective, setting evaluation criteria, establishing a fuzzy judgment matrix and weight vector, and...
This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and...
Workflow planning is a critical stage in new product development (NPD). Based on graph theory and design structure matrix (DSM), this paper presents a systematic workflow planning method for optimizing new product development from an informational structure perspective. Focused on coupling and decoupling theses in concurrent engineering (CE), the workflow planning was divided into two phases of activities...
For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance...
With network time coming, Taiwan enterprises' production. A information system is transforming from OEM to ODM. This research presents a digitalized process model of the product data based on the theories of “Product Design Information” and “E-commerce Design Service”. It can integrate the systems of product design, service and sales as a digitalized EPC system by the supporting of “Product Knowledge...
The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary...
Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
Sub-30 nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30 nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory...
As there are more and more online stores and shopping sites available on the Web, integration of product and shopping information provided by different sources has become more and more important, and attract attention of recent research in information integration. One of the fundamental problems is to integrate specifications for products of the same type from difference vendors so that they are described...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.