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As VLSI technology scales into sub-65 nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode...
We study the applications of the network coding technique for interconnect optimization and improving the routability of VLSI designs. Network coding technique generalizes the traditional routing approach by enabling the intermediate nodes to generate new signals by combining the signals received over their incoming wires. This is in contrast to the traditional (routing) approach, in which each intermediate...
In nanometer regime, IC designers are struggling between significant variation effects and tight power constraints. The conventional approach - using timing safety margin, consumes power continuously to guard against low probability timing variations. Such power inefficiency is largely eliminated in the Razor technology which detects and corrects variation induced timing errors at runtime. However,...
This paper presents a class of power grid analysis and optimization techniques, all of which are based on the algebraic-multigrid (AMG) method. First, a new AMG-based reduction scheme is proposed to improve the efficiency of reducing the problem size for power grid analysis and optimization. Next, with the proposed reduction technique, a fast transient-analysis method is developed and extended to...
Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clock distribution network augmentation for guaranteed skew yield. We present theoretical analysis results on an inserted link in a clock network, which scales down local skew and skew variation, but may not guarantee global skew and...
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