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This paper presents the design and experimental verification of a W-band phase-locked loop (PLL) realized in 65-nm digital CMOS process. The PLL incorporates the proposed divide-by-three frequency divider to relax the power/speed requirement for the succeeding divider chain. A distributed-LC tank is employed in the VCO as well, improving the tank quality factor and the circuit speed. Thus, the power...
A 77 GHz fully-integrated power amplifier (PA) with 50 Ω input and output matching has been realized in a general purpose 90 nm CMOS technology. In order to improve the output power and reduce the signal loss, a transformer and a short stub topology are employed respectively. The power amplifier achieves a saturated output power (Pout,sat) of +13.2 dBm and 1dB compressed output power (Pout,1dB) of...
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