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Through silicon measurements of test chips designed based on two standard cell libraries in 40nm, this paper shows that by proper current distribution balancing between NMOS and PMOS network, standard cells can be improved in terms of speed, power efficiency and variation resilience in sub-threshold region. Compared to the commercial library cells, combinational cells have 2× better speed at sub-threshold...
Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations...
Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. The main drawbacks are performance degradation due to the exponentially reduced driving current, and the effect of increased sensitivity to process variation. To obtain energy savings while reducing performance degradation, we propose the design of a robust sub-threshold library and post-silicon...
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