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We consider technology mapping from factored form (binary leaf-DAG) to lookup tables (LUTs), such as those found in field programmable gate arrays. Polynomial time algorithms exist for (in the worst case) optimal mapping of a single-output function. The worst case occurs when the leaf-DAG is a tree. Previous results gave a tight upper bound on the number of LUTs required for LUTs with up to 5 inputs...
We give three new algorithms to compute tests for faults in the interconnects of random access memories (RAM) using only read and write operations. Diagnosis of address line faults is the most difficult step. Our Adaptive Diagnosis Algorithm (ADA) considers each address line separately. Single line faults are easy to diagnose, so the objective is to ascertain which address lines are free of faults,...
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