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We demonstrate the smallest FinFET SRAM cell size of 0.063 μm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation...
Formation of ultra shallow junctions (USJ) with sufficiently low resistance in the source/drain extension (SDE) region is necessary for MOSFETs at the 45-nm node and beyond. Several doping technologies, such as plamsa doping, cluster ion implantation and gas cluster ion beam (GCIB) doping have been studied as possible replacements for conventional sub-keV ion implantation. In this work we used GCIB...
A novel junction engineering scheme using the combination of LSA and spike-RTA is demonstrated. Xj-Rs tradeoffs of BF2-SDE are investigated for several combinations of spike-RTA and LSA, and it is demonstrated that LSA-first process is effective for the control of the gate-SDE overlap with shallow and low-resistance SDE. This is because dopant impurities are highly activated first by LSA and diffuse...
For the 45 nm beyond advanced LSI mass-production, accurate dose and beam angle control for the implantation process is highly required. For the purpose the ion beam size and angle monitor was developed and installed in EXCEEDS 000AH new version medium current ion implanter.. The measured results shows the beam size and angle increased at the beam energy decreased, especially for the Y direction beam...
A technique for optimizing ultra-thin (EOT ~ 1.1-1.3 nm) SiON gate dielectrics independently for n- and p-MOSFETs is demonstrated. Selective nitrogen-enrichment for the nMOS and fluorine incorporation to the pMOS regions were both performed by ion implantation into the Si-substrate with resist masks before gate oxidation. The former provided suppression of gate leakage current and enhancement of drain...
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