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Critical switching current, Isw, of STT (Spin Transfer Torque)-MRAM has been reduced by several orders with perpendicular MTJ and the state-of-the-art write charge, Qw, becomes the order of 100–150fC. With the small Qw, MRAM starts to save energy consumption by 70–80% compared with a conventional memory system. Analysis of the write pulse-width dependence of Iw revealed a further potential of perpendicular...
Critical switching current, Isw, of STT (Spin Transfer Torque)-MRAM has been reduced by several orders with perpendicular MTJ and the state-of-the-art write charge, Qw, becomes the order of 100–150fC. With the small Qw, MRAM starts to save energy consumption by 70–80% compared with a conventional memory system. Analysis of the write pulse-width dependence of Iw revealed a further potential of perpendicular...
A new FPGA design using nonvolatile configuration memory (NCM) has been presented. NCM with large On/Off resistance ratio, such as nanoionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Unlike previous FPGAs with nonvolatile programmable wires, we took architecture based...
We present a ROM-based 16 times 16 multiplier for low-power applications. The design uses sixteen 4 times 4 ROM-based multiplier blocks followed by carry-save adders and a final carry-select adder (all ROM-based) to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance. Measurement...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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