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Chapter 3 discusses the architecture of the sub-ADCs, which are used in the time-interleaved ADC. A Successive Approximation ADC (SA-ADC) can have a very good power efficiency, its sample-rate is however limited. In a conventional SA-ADC, the sample-rate is mainly limited by settling of the DAC. Overrange techniques can reduce the required DAC settling time. A new overrange technique is presented...
Chapter 4 describes the actual implementation of a high-speed time-interleaved ADC based on the design choices described in this book. Since timing calibration is hard to implement, a switch-driver circuit with low skew is introduced, such that timing calibration is not needed. The sub-ADCs consist of two 6 bits SA-ADCs, a DAC and an amplifier to achieve a good power efficiency, while increasing...
The last chapter summarizes and concludes the book. A per chapter summary is given and the main conclusions and original contributions are presented. The chapter ends with some recommendations for future research.
Chapter 2 describes the Track and Hold (T&H) architecture for a time-interleaved ADC. Mismatch between channels, like difference in offset, gain and timing, degrades the performance and therefore this topic is investigated in detail. Two T&H architectures are discussed, one with a frontend sampler and one without. The use of a frontend sampler has the advantage of good timing alignment...
We live in an analog world, whereas signal processing performed in the digital domain has many advantages regarding noise immunity, accuracy and flexibility. Moreover, its power consumption decreases rapidly as technology shrinks to smaller feature sizes. Together with the increasing system requirements, this creates a large demand for ADCs with a high sample-rate, high resolution and low power consumption...
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which...
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