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Network-on-Chip (NoC) is widely used as a communication scheme in modern many-core systems. To guarantee the reliability of communication, effective fault tolerant techniques are critical for an NoC. In this paper, a novel fault tolerant architecture employing redundant routers is proposed to maintain the functionality of a network in the presence of failures. This architecture consists of a mesh...
We present a concise, fast, accurate, efficient mixed-level full-system based realistic application-oriented simulation platform in this paper which aims to evaluate the cycle-accurate behavior of interconnection component thus help developers to explore more optimized NoC architecture. A trace-driven transaction-level simulation environment is built to get realistic traffic patterns for interconnection...
Networks-on-Chip (NoC) is the promising communication architecture for next generation SoC. The buffer size of on-chip router impacts the silicon area and power consumption dominantly. Optimizing the buffer usage is important for an efficient NoC design. In this paper, we propose an buffer optimization algorithm for application-specific NoC design. More precisely, given the application traffic parameters...
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