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Traditional detection countermeasures against fault attacks have been criticized as insecure because of the fragile comparison operation that can be maliciously bypassed. In order to avoid the comparison, infection countermeasures have been designed to confuse the faulty ciphertexts so that the output cannot be further explored. This paper presents an infection method that resists fault attacks using...
Recent years, lane detection has become of high interest in the area of intelligent vehicles and it provides the fundamental information which can be applied to the further development of Driving Assistance System. In this paper, we propose a lane detection system based on iterative searching and Random Sample Consensus (RANSAC) curve fitting. Experimental results show the effectiveness of our approach...
The coarse-grained reconfigurable architecture (CGRA) is a promising platform that provides both high performance and high power-efficiency. The compute-intensive portions of an application (e.g. loops) are often mapped onto CGRA for acceleration. To optimize the mapping of loop nests to CGRA, this paper makes two contributions: i) Establishing a precise CGRA performance model and formulating the...
Networks-on-Chip (NoC) is the promising communication architecture for next generation SoC. The buffer size of on-chip router impacts the silicon area and power consumption dominantly. Optimizing the buffer usage is important for an efficient NoC design. In this paper, we propose an buffer optimization algorithm for application-specific NoC design. More precisely, given the application traffic parameters...
This paper proposes a novel VLSI architecture of an embedded coarse-grained reconfigurable processor, which consists of a general processor and a coarse-grained reconfigurable cell array (RCA). This processor can be reconfigured dynamically targeted at different media-processing applications. An algorithm based on loop pipeline technology is presented to address the compilation issue for the proposed...
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