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The performance requirements of next-generation CMOS image sensors (CIS) have been increasing in terms of frame rate, read noise, dynamic range, as well as pixel resolution. In order to satisfy strict specifications, a column-parallel ADC is a key element in a state-of-the-art CIS. However, this architecture leads to side-effects such as vertical fixed pattern noise (VFPN) and read noise. In order...
A 15 b power-efficient pipeline A/D converter using capacitance-coupling non-slewing amplifiers is presented. A modified 1.5b/stage transfer curve combined with the non-slewing amplifier is useful for the error corrections of incomplete settling error. The relationship between the input signal and the incomplete settling errors can be linearized and the errors can be corrected in digital domain with...
A sampling clock skew calibration method with a new calibration signal addition circuit is presented in this paper. The clock skew is detected using a calibration signal, and the calibration is done by adjustment of sample clock delay. The new calibration signal addition circuit consisting of small capacitors and a few switches has little interference to the input signal, and makes it possible for...
A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.
Timing error between sampling and holding (SZH) channels for Time-interleaved analog-to-digital converts (TiADCs) is caused by clock skew and RC (sampling resistance and capacitance) mismatch. This paper presents the measurement results of a prototype chip based on our previous work (Z. Liu et al., 2006), in which we showed timing error due to clock skew and RC mismatch can be calibrated simultaneously...
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