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This paper presents a design method of reversible integer quaternionic paraunitary filter banks (Int-Q-PUFB) using the adder-based distributed arithmetic (DAΣ) for implementation multiplier block-lifting structure modules. The proposed quaternion multiplier (Q-MUL) and 8-channel Int-Q-PUFB processors are implemented on the FPGA Xilinx Zynq 7010. The total magnitude response of analysis-synthesis system...
This paper presents a systematic design of the integer-to-integer invertible quaternionic multiplier based on the block-lifting structure and pipelined embedded processor of the given multiplier using distributed arithmetic (DA) as a block of M-band linear phase paraunitary filter banks (LP PUFB) based on the quaternionic algebra (Q-PUFB). A bank Q-PUFB based on the DA block-lifting structure reduces...
A new family of the integer-to-integer invertible quaternionic Q-PUFB (Int-Q-PUFB) using multipliers based on the block-lifting structure with the sum-of-power-of-two (SOPOT) coefficients is developed. The design problem of a Q-PUFB is formulated as constrained optimization problem. The modified method of Lagrange multipliers was chosen as optimization method. Design examples show that SOPOT Int-Q-PUFB...
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