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We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipped Voltage Follower (FVF) topology, and compare it with a class-A CCII based on the conventional FVF. The AB-FVF is capable of driving larger capacitive loads, showing faster settling. Furthermore, it can drive the Z output with currents larger than the biasing ones, improving power efficiency. A modification...
A closed-form representation of the reconstruction filters for a 4-channel Time-Interleaved ADC affected by gain mismatches and timing skew is derived solving the Papoulis equations. First-order Taylor expansions of the filters are then computed to enable linear estimation methods to be used in foreground and background calibration techniques. The results are validated with behavioral simulations...
The Voltage Conveyor (VCII) is the dual of the second generation Current Conveyor (CCII), and has received only a cursory attention in the literature, probably for lack of interesting applications. The VCII has a current buffer between Y and X terminals, and a voltage buffer between X and Z terminals. In this way, it makes it easier to sum (current) signals at the Y node, whereas CCIIs make it easier...
The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and better numerical properties. We propose a VHDL implementation that has been successfully implemented on a Xilinx Virtex-7 FPGA. The FWL RLS algorithm has a complexity of L2 + O(L) products, instead of 1.5L2 O(L) as in conventional RLS algorithms. Because...
Conventional Recursive Least Squares (RLS) filters have a complexity of 1.5L2 products per sample, where L is the number of parameters in the least squares model. The recently published FWL RLS algorithm has a complexity of L2, about 33% lower. We present an algorithm which has a complexity between 5L2/6 and L2/2. The algorithm is in theory as fast and accurate as the other RLS ones, but employs a...
An analytical model to evaluate the hybrid architecture of a wide bandwidth high-speed digitizer is proposed. The model is based on the robust approach of multi-rate signal processing theory and allows analyzing the effects of the impairments that can affect the digitizer, and consequently evaluating achievable performance. The proposed model can also be used at design stage to identify viable solutions...
Digital IF receivers face a trade-off between the required selectivity of the frequency response and the value of the IF frequency: higher IF frequencies make it easier to reject the image frequency of the mixer, but increase the required Q values in the anti-aliasing filter. However, high-Q filters are hard to implement in IC technologies. The conventional approach to filter design is to convert...
A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has...
A novel architecture for optical beamforming is presented, and its implementation as an integrated multi-chip system is discussed. Modeling and design methodology of the key components of the system, i.e. the linearized electro-optic external modulator and the array of tunable true delay lines, is detailed. Measurements on a linearized modulator are presented to demonstrate the feasibility of the...
This paper investigates the implementation of radar algorithms on Graphics Processing Units (GPUs). The focus is on electronically scanned search radars. GPUs enable to develop high performance digital processing systems with limited development time. It is possible to employ a single commercial board (an NVIDIA GeForce 680 GTX in our case) to perform all the algorithms of a search radar: downconversion,...
We analyze the effects of relative mismatches in transconductances and in capacitances onto the magnitude of the Gm-C biquad filter section. It is confirmed that deviation from the ideal magnitude increases with Q and with mismatches, being those associated with transcondunctances the relevant ones. The obtained data can be used at an early design stage to limit the magnitude error of a cascaded filter...
An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high-precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opamp and of the opamp used in the voltage follower is...
In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter,...
In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage...
This paper presents a design procedure for high-order continuous time low-pass filters based on the cascade of biquadratic cells. The proposed approach is amenable for integration, as it takes into account the maximum capacitance spread imposed by the available technology, and also allows a tradeoff between noise and maximum linear range to be met, thereby improving the dynamic range. Simulations...
In this paper we present a low-power low-voltage class-AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage can be used. The two SHAs have a nominal gain...
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