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This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time domain 5-bit sequence including MSB and LSB. The architecture also enables built-in error correction with very low latency. This concept is demonstrated with prototype implemented in a 28nm FDSOI CMOS using only 18-data comparators...
A low power channel adaptive 28 Gb/s PAM-4 receiver is presented utilizing a predictive ADC, a SAR TDC, and an FFE in digital domain. The variable resolution Flash ADC can provide 5.5-bit resolution using only 16 comparators taking advantage of the channel ISI. The ADC resolution is programmable from 2-bit to 5.5-bit consuming 40mW to 90mW respectively. The SAR TDC generates 5-bit output with 2-bit...
This paper presents a low power clocking solution for multi-standard SerDes applications based on frac-N digital LC PLL for central clock generation and fractional-N ring PLL for local clock generation. The fractional-N LC PLL operates at 7–10 GHz consuming only 8 mW power and occupying 0.15 mm2 of silicon area with integrated jitter of 264 fs. Ring PLL covers from 800 MHz to 4 GHz to support the...
Intersubband transitions in quantum cascade heterostructures have been proposed for thermo-photovoltaic energy conversion for applications in solar cells so that when they are used cascaded with p-n junctions efficiency can be increased. Our designed structures produce wider absorption spectra and faster carrier transport than those have been reported before.
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