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LDPC coding has attracted much attention due to its high performance, and it has been widely used in telecommunication systems. This paper focuses on the decoder hardware architecture, especially on memory size reduction, which is an important part of the entire area cost. The design has been post-layout simulated using a UMC 0.18 micron technology at a clock speed of 74 MHz. Using the proposed 3-level...
In this paper, we present an improved algorithm for super-resolution image restoration which used L-Curve regularization to Maximum A-Posteriori method. Super-Resolution as the second-generation problem of image restoration is also an ill-posed question because of an insufficient number of LR images and ill-conditioned blur operators. Procedures adopted to stabilize the inversion of ill-posed problem...
An efficient and configurable computational platform is indispensable in order to meet multiple wireless communications standards. We have developed a heterogeneous reconfigurable architecture to support the arithmetic, logic and signal processing functions which are required for transceivers used in standardized wireless local area networks. Each execution unit in this reconfigurable architecture...
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