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Neuromorphic computing takes inspiration from how the brain works to explore novel computing paradigms. Recently, neuromorphic architectures using spiking neurons were proposed for unsupervised learning of pattern- and feature-based representations. These approaches typically use a common WTA architectural motif of lateral inhibition that introduces competition between the neurons. In this paper,...
Neuromorphic systems provide biologically inspired methods of computing, alternative to the classical von Neumann approach. In these systems, computation is performed by a network of spiking neurons controlled by the values of their synaptic weights, which are updated in the process of learning. Providing efficient synaptic learning rules, such as spike-timing-dependent plasticity (STDP), is a challenging...
An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise...
Hardware security in server, client, mobile and embedded systems is becoming increasingly critical, especially with the rapid growth of the Internetof- Everything (IoE). Security threats and vulnerabilities for all hardware components must be addressed. This forum brings together chip designers and system architects to discuss: (1) design, hardware and logistics attack challenges, as well as advanced...
In this paper we present the design of a programmable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide-by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation...
In this paper we present the design of a temperature compensated low-tune-voltage-sensitive CMOS ring oscillator in 40nm standard CMOS technology. The oscillator has an overall frequency range from 3.1 GHz to 3.6 GHz. The effect of temperature variations on the frequency span has been tuned out by an IPTAT (inversely proportional to absolute temperature) current reference. In this work, using a coarse-fine...
An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk)...
This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. The proposed trinocular DE hardware is the enhanced version of the recently published binocular AWDE implementation. The T-AWDE hardware generates...
Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply dual in-line memory modules (DIMMs) because of their high capacity and low cost. However, the multi-drop bus (MDB) interface between these units...
An innovative readout channel, based on analog amplitude modulation of the signals recorded by each sensing site, is developed for high-density CMOS-based microelectrode arrays. A single amplification stage simultaneously records the neural activity acquired from several sensors. A theoretical analysis has demonstrated that a major physical limitation of the readout architecture relates to the summation...
This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel...
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