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In design and implementation of energy efficient counter for energy efficient processor, we are using LVCMOS I/O standard in FPGA. CMOS technology is used to achieve energy efficiency with corresponding low voltage. We observe that when counter operates at 1×106MHz device operating frequency, there is 67.42% reduction in clock power and 75.99% reduction in IO power with LVCMOS I/O Standard. In counter,...
In this work, clock gating technique is applied on the Frame Buffers in order to get more energy efficient Frame Buffers. Frame Buffer is an in-built memory of digital Image Processor, which is writeable by the CPU and readable by the Video Interface and used to store color of each pixel. Clock gating is a power saving technique which turns off the inactive component of design in order to save power...
In this work, Capacitance scaling and Frequency scaling is done in order to make energy efficient Image Inverter design. Frequency scaling results variations in power consumption and the Junction temperature of Image Inverter. There is 93.33% change in Logic power, 98.06% change in Signals power, 99.00%change in IOs power, 92.02% change in Leakage power and 77.6% change in Junction temperature. Clocks...
In this work, target design is ALU. To achieve reduction in IOs power we are searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard. There is 85.18% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS12 based ALU design. There is 41.45% power reduction when we...
This paper proposes design of frame buffer for a digital image processor. This design is implemented on Virtex-6 Field Programmable Gate Array (FPGA). In this work, three classes of High-Speed Low Voltage Digitally Controlled Impedance (HSLVDCI) are used to compare dynamic power requirements for the frame buffer. The experiment is performed at 1 GHz, 10 GHz, and 100 GHz and 1 THz device frequencies...
In this paper, green Image ALU is designed in Xilinx ISE 14.6 using LVDCI(Low Voltage Digitally Control Impedance) and LVDCI_DV2(Half Impedance Version of LVDCI) I/O standard in 40nm Virtex-6 FPGA. By using LVDCI technology we achieve energy efficiency with respect to low voltage impedance. In this whole work, we are using three different classes of LVDCI and LLVDCI_DV2 and observe that when image...
To make smart card much faster, we need efficient data structure. Access time of on chip data depends on how and where we stored. Some Data Structure take maximum time and some take minimum time depending on the space and time complexity of data structure. In this work, we have taken some data structures and find that BST is the best suitable data structure for performing smart card operations in...
In this work, we are using Stub Series Transistor Logic (SSTL) on the simplest VLSI circuit multiplexer and analyze the power dissipation with different class. Using SSTL15 in place of SSTL2_II_DCI, there is reduction of 304mW power i.e. 76.19% power reduction. Using HSTL_I_12 in place of HSTL_III_DCI_18, there is reduction of 157mW power i.e. 62.3% power reduction. HSTL and SSTL are IO standards...
In this paper, we apply clock gating technique in Global Reset ALU design on 28nm Artix7 FPGA to save dynamic and clock power both. This technique is simulated in Xilinx14.3 tool and implemented on 28nm Artix7 XC7A200T FFG1156-1 FPGA. When clock gating technique is not applied clock power contributes 32.25%, 4.24%, 3.06%, 3.09%, and 3.09% of overall dynamic power on 100 MHz, 1 GHz, 10 GHz, 100GHz...
This paper, deals with Latch Free Clock Gating technique for reduction of clock power and dynamic power consumption in ITC'99 bo1 Benchmark circuit and we have compared power reduction at different device operating frequencies. Without latch free clock gating technique in b01 benchmark circuit the Contribution of Clock power was 37.50%, 37.64%, 4.46%, 38.75% and 38.76% of total dynamic power when...
Performance is a critical issue in setup of network center in any academia. In a research institute, a moment of time is precious for analysis, design, research and development. In this work, an efficient approach, which based on firewall, complaint handling system, LDAP server and spanning tree protocol, is used to set up a network center in ABV-IIITM to provide network facility to researcher, student...
In this paper the effect of back off factor on exponential algorithm is analyzed and binary exponential algorithm is implemented in Mat lab. Binary Exponential Algorithm is widely used as a network congestion avoidance or collision resolution protocol. The detailed analysis of saturation throughput is done in this work. This work also covers packet's medium access delay for a given number of node...
In this work, Virtex-6 is Target 40nm FPGA Device. Xilinx ISE 14.1 is an ISE Design tool. RAM is a target design. Clock Gating is a technique which decreases clock power but increases Logic Power due to added Logic in Design. Irrespective of increase in number of Signal and IO buffer due to Clock Gating, there is significant decrease in IO Power and Dynamic Power due to decrease in number of frequency...
Here, assumption is that if we add 8 numbers from register array then it takes 120ns when execution time is 5ns and register access time is 10ns. If we add same 8 number using one by one fetching from memory then it takes 840ns to add 8 numbers. In that way we are saving 720ns, i.e., 85.7% time saving in execution of add instruction to add 8 numbers. In this way, our Instruction Set based on Flag...
In this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE 14.2 and implemented on high performance Virtex-6 FPGA, XC6VLX240T device, -1 speed grade, FFG1156 package and ML605 board. User constraints file (ucf) and net list constraints design (ncd) file are taken into consideration with XPower 14.2 for power consumption analysis. We take two...
In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. Virtex-6 is 40-nm FPGA, on which we implement our circuit to re-assure power reduction in sequential circuit. Clock gating is implemented on smaller circuit called D flip-flop and on larger circuit called 16-bit register. The percentage...
In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard implementation on input or output port in...
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