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Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for...
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market from medium to high resolution ADCs. Due to its low power, high-performance and small area in Mega-Hz range, SAR ADCs are increasingly attractive for todays safe-critical applications like automotive. Recently, much research has been carried out on self-calibrations of SAR ADCs, which...
A major threat in extremely dependable high-end process node integrated systems in e.g. Avionics are no failures found (NFF). One category of NFFs is the intermittent resistive fault, often originating from bad (e.g. Via or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects...
This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic...
This paper presents a technique for reducing CPU time to perform simulation-based fault-injection experiments in complex SoCs. This technique is fully compatible with commercial HDL simulators with no requirement to develop dedicated compilers. This approach can be easily applied to complex SoC models, as it is not required to modify the top-level modules of design, moreover, it can inject a wide...
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