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In current VLSI complexity systems, clock skew scheduling is one of the key approaches to improve circuit performance and reliability. A delay insertion method has been discussed in logic-level to reduce the clock period. This paper extends this idea into high-level synthesis (HLS), and introduces a new HLS task, namely the minimum-path delay assignment. Since register binding plays an important role...
Recently, latch-based design has attracted attention due to its several merits. Time borrowing is one feature of latches, where a slower functional unit can borrow timing slacks from a faster functional unit. This paper shows that latency can be reduced by integrating the time borrowing into operation scheduling in latch-based design. Specifically, continuous execution delay model is adapted to operation...
This paper proposes a novel high-level synthesis (HLS) using double-edge-triggered flip-flops (DETFF) as memory elements. The duty-cycle is a key factor in the HLS. To utilize the duty-cycle radically, a variable-duty-cycle (VDC) mechanism is built into the HLS, which is captured by a new HLS task named VDC scheduling. As the first step for DETFF-based HLS, the clock-period minimization problem is...
As the feature size of transistors becomes smaller, delay variations become a serious problem in VLSI design. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. One approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path...
In many synthesis approaches, scheduling is completed before resource binding. Binding centric approaches and simultaneous scheduling/binding approaches such as 3D scheduling are alternative approaches to the high level synthesis. In those approaches, binding is often performed before completion of scheduling. The objective of this paper is to identify and characterize a "feasible" resource...
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