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The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units...
The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure, hi this paper,...
In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that the register binding in high-level synthesis...
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