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With the advent of deep sub micron era, design closure is becoming harder to achieve. In high-level synthesis, slack is a very effective means of tolerating uncertainties. Thus, several research efforts have been paid to study the slack-driven high-level synthesis problem. However, previous works cannot actually maximize the total slack value, because they are limited to either the operation scheduling...
Although clock skew can be utilized to reduce the clock period, the utilization of clock skew also limits the sharing of resources (including registers and functional units). Previous works have considered the influence of clock arrival times on register sharing, but they do not pay any attention to the influence of clock arrival times on functional unit sharing. As a result, extra functional units...
In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle...
Power gating is the most effective technique to reduce the leakage power of an idle functional unit. However, when the functional unit is turned on, a sudden discharge, called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In this paper, we point out the high-level synthesis...
The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units...
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