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This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current ($I_{\mathrm{\scriptscriptstyle OFF}})$ of 50-nm Ge-pTFETs to...
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