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This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors...
Subthreshold design method is a prominent method for designing of ultra-low power design methods. SRAM is an significant component in these systems consuming significant portion under power budget. Operation of 6T SRAM at sub or near-threshold voltages is unfeasible, due to degraded static noise margins (SNM) and poor robustness. In this paper, we analyze various alternative SRAM bit cells such as...
Ultra Low Power is the is one of the prominent technology in the VLSI Industry. One of the technique is used to improve Sub-threshold Logic Design. This technique is used to model the ultra-low power application design. This paper offers Sub-threshold logic for memory devices such as Static RAM and observed the power consumption (PC), leakage power(PL) and delay for different SRAM Bit models of 6T,...
Resource sharing is a very efficient mechanism to reduce FPGA resources for realizing several application categories. In the context of realizing signal processing datapath in area efficient applications several researchers attempted to Resource sharing. The present work demonstrates realizing FSK receiver on small Xilinx FPGA. In this work FSK demodulator architecture is simulated using MATLAB tool...
Winner Take all circuits are widely used in hardware implementation of pattern recognition systems based on Hamming Neural Network. WTA is a kind of competitive network which takes voltage or current as its input. The WTA function is to accept input signals from outer world, compare all the received inputs, largest intensity signal is accepted by WTA and assign a high digital value to corresponding...
A pipelined parallel processing 3D DWT architecture is designed in this paper based on lifting scheme algorithm with 9/7 wavelet filters. The 3D DWT architecture process a 512×512 image with 8 groups of frames sequentially with improved throughput. The first stage computes 1D-DWT along the rows with 4 parallel processors, the memory interface with FIFO reduces latency between first stage and second...
Reversible logic gates became very important and computing paradigm having its applications in low power CMOS technologies and Quantum computing [5]. Reversible logics are used to reduce the depth of the circuits [6]. This paper introduces a new architecture of 4:2 Compressor based Vedic 8×8 bit Multiplier using reversible logic and is compared with conventional multipliers using Reversible logic...
The memories are more and more used as an embedded element rather as a separate block. Being used as a macro, its user has nothing to change or optimize. So, the design of memory needs to address all the issues specially to optimize the rigorous area and power requirements. This paper discusses the issues in design of SRAM memory cell for low power applications. 6T architecture SRAM cell is taken...
Research on run time reconfiguration of FPGAs has been in academia for more than two decades, attempting to derive more benefits for FPGA based designs. The Dynamic Partial Reconfiguration (DPR) with runtime partial bit file loading capability was found to be more useful for designing flexible hardware. Majority of researchers found the limitations with DPR approach, due to higher configuration time...
As silicon semiconductor device feature size scales down to the nanometer range, planar bulk CMOS design and fabrication encounter significant challenges nowadays. Carbon Nanotube Field Effect Transistor (CNTFET) has been introduced for high stability, high performance and low power SRAM cell design as an alternative material. Technology scaling demands a decrease in both VDD and VT to sustain historical...
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube FETs (CNTFETs) are considered to be the possible “ beyond CMOS” device due to its 1-D transport properties that include low carrier scattering and ballistic transport. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most...
As technology scales down both VDD and Vt has to decrease to maintain historical delay reduction, while restraining active power dissipation. Scaling of Vt however leads to substantial increase in the sub-threshold leakage power and it became a considerable constituent of the total dissipated power. Nowadays leakage power is the dominant component of the total power so it's become important issue...
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